1. Field of the Invention
Embodiments of the present invention relate to techniques for marking cache lines. More specifically, embodiments of the present invention relate to a technique for tracking load-marks and store-marks on cache lines to prevent interfering accesses by other threads.
2. Related Art
Some computer systems have been designed to place load-marks and/or store-marks on cache lines that are accessed by a thread (also called a “strand”) to prevent interfering accesses to the cache line by other threads. For example, if a thread needs to ensure that it can read from a cache line without another thread storing a value to the cache line, the thread can place a load-mark on the cache line to prevent another thread from storing a value to the cache line. The load-marking process is described in more detail in U.S. patent application Ser. No. 11/591,225, entitled “Facilitating Load Reordering through Cacheline Marking,” by inventors Robert Cypher and Shailender Chaudhry. Similarly, the process of placing store-marks on cache lines to prevent subsequent interfering accesses to the cache lines is described in more detail in U.S. patent application Ser. No. 11/591,223, entitled “Facilitating Store Reordering through Cacheline Marking,” by inventors Robert E. Cypher and Shailender Chaudhry.
In some of these systems, a thread is limited to placing one load-mark and/or store-mark on a given cache line. Hence, the thread must remove any existing marks from the cache line before placing any subsequent marks on the cache line. In addition, the system is required to remove marks from cache lines when the marks are no longer needed. For example, the thread must remove load-marks and/or store-marks from cache lines after completing a “phase of operation” wherein related load-marks and/or store marks are placed on cache lines.
Some systems use a private buffer to keep track of the addresses of cache lines that a thread has marked. In these systems, when a cache line is load-marked and/or store-marked, an entry is added to a private buffer for the thread, wherein the entry includes information about the load-mark or store-mark such as the address of the cache line where the load-mark and/or store-mark was placed.
While removing load-marks and/or store-marks from cache lines, the system examines the entries in the private buffer to identify the cache lines from which load-marks and/or store-marks must be removed. After removing the mark(s) from a given cache line, the thread removes the associated entry from the private buffer.
In some systems, threads quickly transition between different phases of operation, which for example can be different transactions. In these systems, thread performance can be hampered by the requirement that the system remove load-marks and store-marks for the thread after each phase of operation. For example, if the system is still using the entries in the private buffer to remove load-marks and/or store-marks from a preceding phase of operation, the system may not be able to place entries for newly marked cache lines into the private buffer. Consequently, the system may not be able to place load-marks and/or store-marks on cache lines for the thread, which can impede the performance of the thread.
Hence, what is needed is a system that supports load-marking and store-marking of cache lines without the above-described problems.